| Ref. : Universal Asynchronous Receiver / Transmitter with FIFO »


– Single-chip synchronous UART
– Designed to be included in high-speed and high-performance applications
– Very fast system clock frequency (FPGA speed grade dependant)
– CPU independent interface
– Complete asynchronous communication protocol including :
* 5,6,7 or 8-bit data transmission

* Even/Odd or no parity bit generation and detection

* Start and Stop bit generation and detection

* Line break generation and detection

* Receiver Overrun and framing detection
– High baud rate (system frequency dependent)
– 1 to 65535 divisor generates 16X clock
– Register and FIFO mode
– Buffered transmit and receive registers
– Transmitter and receiver are buffered with 16 Byte FIFO, plus 3 error bits per data byte on receiver
– Polled or interrupt modeLoopback mode
– DO254 Documentation available


General Description

The macro MUART, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a serial communication channel. This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.