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M16550

M16550

| Ref. : Universal Asynchronous Receiver Transmitter with FIFO »

Features                                                                                                                                                                               

 – Single-chip synchronous UART

 – Functionally based on the National Semiconductor Corporation NS16550 device 

 – Designed to be included in high-speed and high-performance applications
 – Very fast system clock frequency (FPGA speed grade dependant)
 – CPU independent interface
 – Complete asynchronous communication protocol including :
* 5,6,7 or 8-bit data transmission

* Even/Odd or no parity bit generation and detection

* Start and Stop bit generation and detection

* Line break generation and detection

* Receiver Overrun and framing detection

– Up to 1M baud (system frequency dependent)
 – 1 to 65535 divisor generates 16X clock
 – Buffered transmit and receive registers
 – Transmitter and receiver are buffered with 16 Byte FIFO, plus 3 error bits per data byte on receiver
 – Polled or interrupt modeLoopback mode

General Description
The M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a serial communication channel. This IP can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.