The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is compliant with Serial ATA II specification and signaling rate is GEN1 and scalable to GEN2. The LDS SATA HOST XV5 IP is fully synchronous with system frequency (Clock_sys) at 37.5MHz in case of GEN1 speed selection and 75MHz in case of GEN 2 speed selection. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request. This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.