The LDS_SATA3_DEVICE_XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The LDS_SATA_DEVICE_XK7 IP is compliant with Serial ATA III specification and signaling rate is 3Gbps and scalable 6Gbs. The LDS_SATA_DEVICE_XK7 IP is fully synchronous with system frequency (Clock_sys) at 75MHz in case of 3Gbps speed selection and 150MHz in case of 6Gbs speed selection. The source code format is available for ease of customization. Ie can be customized by Logic Design Solutions and DO254 documentation is available on request.