The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA Cyclone V GX FPGA. The LDS SATA 2 HOST C5GX IP is compliant with Serial ATA II specification and signaling rate is 3Gbps and scalable 1.5Gbs. The LDS_SATA2_HOST_C5GX IP is fully synchronous with system frequency (Clock_sys) at 75MHz in case of 3Gbps speed and 37.5MHz in case of 1.5Gbs speed configuration. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.