Features
– Single-chip synchronous UART
– Functionally based on the National Semiconductor Corporation NS16450 device
– Designed to be included in high-speed and high-performance applications
– System clock up to 150 MHz
– CPU independent
– Complete asynchronous communication protocol including :
– 5,6,7 or 8-bit data transmission
– Even/Odd or no parity bit generation and detection
– Start and Stop bit generation and detection
– Line break generation and detection
– Receiver Overrun and framing detection
– Up to 1M baud (system frequency dependent)
– 1 to 65535 divisor generates 16X clock
– Buffered transmit and receive registers
– Polled or interrupt mode
– Loopback mode
General Description
The M16450, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a serial communication channel.
This IP can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.