The LDS SATA 3 HOST AR5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Stratix IV GX FPGA. The LDS SATA 3 HOST AR5GX IP is compliant with Serial ATA III specification and signaling rate is 6Gbps and scalable 3Gbs. The LDS SATA 3 HOST AR5GX X IP is fully synchronous with system frequency (Clock_sys) at 150MHz in case of 6Gbps speed selection and 75MHz in case of 3Gbs speed configuration. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.