The M429GEN IP implements a synchronous single-chip ARINC 429 Transmit and Receive Controller capable of linking one CPU to one or several  ARINC 429 bus. The IP controls all ARINC 429 bus specific sequences, protocol and timing. The M429GEN IP interface allows the parallel-bus microprocessor to communicate bidirectionally with the ARINC 429 bus.

• Independent Receivers (Rx) with FIFO
• Independent Transmitter (Tx) with FIFO
• Number of RX and TX line defined by Generics
• Decoding signals interface type
• AXI-Lite Data-bus
• ARINC 429 Interface : ‘1’ and ‘0’ Lines, RZ code
• Support all ARINC 429 Data Rate Transfer and up to 2.5 Mbit/s
• Multi Label Capability
• Parity Control : Odd, Even, No Parity, Interrupt Capability
• Independent Interrupt Request for Rx and Tx Functions
• FPGA speed grade operating frequency dependant
• Available in VHDL source code format for ease of customization
• DO254 design, verification and traceability documentation available on request
• Can be customized by Logic Design Solutions

This IP can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.