Logic Design Solutions launches the first NVMe HOST IP on POLARFIRE SoC FPGA

Targeting embedded recorder systems: NVME-HOST-RECORDER-PFSOC IP

France, Gournay sur Marne, April 12th 2021 – Logic Design Solutions (LDS) extends its portfolio of NVME-HOST IPs with the first NVME-HOST IP on POLARFIRE SoC FPGA which enables designers to address specific market in embedded recording domain.

Higher performance                                                                                                                                                                                                                                                                                                                                                                                                                                                                              MVMe disks can manage several PCIe links, which allows them to reach recording speed faster than SATA disk, which have only one link running at 6Gbits maximum, allowing them a recording speed of 500 MBytes/sec.                                                                                                                                          Nevertheless in some cases, SATA disk in RAID 0 can compete NVMe disks in writing and reading speed and in capacity, but at the expense obviously of a need for more space.

Simple to use                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          LDS, has for many years acquired expertise in the field of embedded recording, so LDS has taken care to offer an NVMe IP which is easy to use for both those who start in the field of NVMe disks and the more experienced.  Thus all the NVMe protocol is managed by the IP, which is connected to an embedded PCIe Root Port IP in the FPGA. Configuration of the PCIe and of the NVMe are done automatically when power is turned on or on demand after a disk shutdown procedure. The configuration of the recording session is done by writing to IP registers, using an APB bus. All other data buses are in AXI4 to facilitate the use of the IP.Thus, the IP is manageable either by a state machine, whose VHDL source code is provided or by a CPU whose C source code is also provided.The user can start his project directly from ones delivered by LDS.