The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.

• The LDS NVME HOST IP provides two interfaces :
  • One CPU interface for long sequential recording or reading.
  • One FIFO interface for I/O intensive data transfer.

The register file interface simplify the management of the IP for CPU interface or State Machine interface using AXI bus:

• PCIe RP and EP register configuration is done automatically.
• NVMe register configuration is done automatically.
• Able to manage 8 Name Spaces.
• Able to manage until 16 IO Queue to able Multi-users.
  • Each IO Queue is independent.
• Able to manage 512Bytes or 4096Bytes sector size.
• Able to run nearly all Admin command in parallel of IO Queue.
• Many IO command already pre-defined to ease use of the IP.
• Configurable IO Queue buffer size to fit user memory requirement in case of small density FPGA: 32KB, 64KB, 128KB, 256KB, 512KB or 1024KB.
• Able to read all PCIe RP and EP registers.
• Able to stop current command.
• Able to manage low data rate in reading.
• Easy connection to embedded Root Port PCIe IP through AXI bus.
• FAT32 / EXFAT available as an option.

When using a PCIe RP IP configured in Gen3 the system frequency is at 125MHz/256-Bits.

When using a PCIe RP IP configured in Gen2 the system frequency is at 125MHz/128-Bits.

The source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.

This IP can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.