The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The LDS SATA HOST AR2GX IP is compliant with Serial ATA II specification and signaling rate is 1.5Gbps and scalable 3Gbs. The LDS_SATA_HOST_AR2GX IP is fully synchronous with system frequency (Clock_sys) at 37.5MHz in case of 1.5Gbps speed selection and 75MHz in case of 3Gbs speed selection. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.