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I2C IP / MI2CMS

MI2CMS | Ref. : I2C Master Slave   » 

MI2CMS

Features

- Single-chip synchronous I2C Master and Slave Macro in FPGA (I2C is a trademark of Philips, Inc)

- Designed to be included in high-speed and high-performance applications

- Direct Connection to CPU register set

- Compliant with I2C-bus specification version 1.0

- Standard mode operation (100Kbits)

- Multi-master operation with arbitration and clock synchronisation (only master)

- Support for reads and writes only

- 7-bit and 10-bits address management

- Synchronised on system clock

- Hardware digital filter on SCL and SDA signals

- No support of general call

- FPGA speed grade operating frequency dependant : system clock up to 180 MHz

- Available in VHDL source code format for ease of customization

- Can be customised by Logic Design Solutions

 

 

General Description

The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using interrupt or polled handshake. It controls all I2C-bus specific sequences, protocol, arbitration and timing. The I2C macro interface allows the parallel-bus microprocessor to communicate bidirectionnally with the I2C-bus.This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.

 

 

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